Created it, 06/09/09
Update it, 06/09/27
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3. - DEAD MEMORIES (ROM)
The ROM memories (Read Only Memories), which only means memory with possible reading, are also called dead memories. Their principal characteristic is to be not bird.
The basic cell of a ROM can be obtained starting from a dynamic storage cell in substituent with the condenser an open circuit or a connection to the mass. It results either state 0 thus from it, or state 1.
Figure 36 represents a read-only memory with 16 bits.
Each storage cell is formed by a diode and a switch which either is opened, or closed.
A closed switch will thus put in electrical contact a line with the column to which it is connected, in condition obviously that the diode which is associated for him is busy. This one will be conducting if its anode is positive, which requires the presence of a level 1 on the outlet side of the buffer of entry, level given by the decoder whose exit will be 1 (decoder at active exits with 1) for the decoded address. An example is given blue color figure 37 for address 112.
The decoder makes correspond to 112 value 310. Exit 3 is thus to 1. One thus obtains at exit D3 = 0 (open I3 switch), D2 = 1 (closed I2 switch), D1 = 1 (closed I1 switch) and finally D0 = 1 bus I0 is closed.
We see that the switches closed for the other lines do not have an influence because the diodes which are associated for them all are blocked.
The table of figure 38 gives the contents of the memory for each of the four addresses (combinations of A0 and A1).
Figure 39 represents the synoptic diagram of a ROM memory structured in eight words of two bits each one, that is to say a capacity of sixteen bits.
For technological reasons, we preserve a square matrix, indeed, this one allows to save on the surface of semiconductor necessary to the construction of such an integrated circuit.
The four bits resulting from the four columns are sent two to two on the entries of two multiplexers two towards one. One can thus obtain at exit eight words of two bits by selecting four lines with either the even columns two and four, or the odd columns one and three.
With this intention, three bits of address now are used. The first two bits A0 and A1 make it possible, like previously, to select the line, whereas the third bit A2 makes it possible to choose either the even columns, or odd columns.
Figure 39 gives an example for the address 0 1 1 (A2 = 0, A1 = 1 and A0 = 1). 0112 is decoded like 310 and it is thus exit 3 of the decoder which is to 1, it then validates the diodes of the third line through the buffer.
The bit A2 being to 0, the multiplexer selects columns 1 and 3 (odd columns). One reads then D1 = 0 and D0 = 1 : routes blue color on figure 39.
The table of figure 40 gives according to the possible addresses, and this for figure 39, the data contained in memory.
The contacts appearing figure 39 are not actually mechanical switches but electric connections intern with the integrated circuit, realized during its manufacture.
The internal provision of the electric connections in question varies at the request of the customer.
To carry out the circuit according to the specifications of his customer, the manufacturer uses a photographic mask on which it adds the desired connections.
However, this type of memory can be provided only in very great quantities, taking into account the high cost of the manufactoring processes calling upon the photoengraving and the chemical attack.
These circuits cost much less than the RAM but the series must comprise a thousand of specimens at least.
3. 1. - EXAMPLE OF ROM
MEMORY
You can see figure 41 the synoptic diagram of a ROM memory of 32K of the type MCM 68 A332 like its stitching.
This type of memory includes/understands inside the same case the decoder of address and the buffers of exit three states.
3. 2. - USE OF ROM MEMORIES IN THE COMBINATIVE CIRCUITS
Taking into account their properties, the ROM memories can, under certain conditions, to replace a combinative circuit.
Indeed, if one compares an address to a whole of variables of entry, one can consider that the data obtained by reading the position memory with the address in question will be the variables of exit of the system.
Figure 42 represents the truth table of a circuit.
| a | b | c | S1 | S2 |
| 0 | 0 | 0 | 0 | 0 |
| 0 | 0 | 1 | 1 | 0 |
| 0 | 1 | 0 | 1 | 0 |
| 0 | 1 | 1 | 1 | 0 |
| 1 | 0 | 0 | 1 | 1 |
| 1 | 0 | 1 | 1 | 0 |
| 1 | 1 | 0 | 0 | 1 |
| 1 | 1 | 1 | 1 | 0 |
It will thus be enough to write in a memory 0 0 with the address 0 0 0, 1 0 with the address 0 0 1, 1 0 with the address 0 1 0, 1 0 with the address 0 1 1, 1 1 with address 1 0 0, 1 0 with address 1 0 1, 0 1 with the address 1 1 0 and 1 0 with the address 1 1 1 to be able to replace the combinative circuit by a ROM.
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