Programmable
Logic Networks |
The
PLA “Programmable Logic Array” |
FPLA |
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FPLA
with Memory |
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Created it, 06/09/09
Update it, 06/09/28
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In the preceding theory, we saw the use which we could make of the ROM memories, to replace a combinative circuit generally formed with logical NAND, NOR doors,….
This technological development in direction of the programmable circuits, already raised during the examination of the multiplexers, led the manufacturers of integrated circuits to carry out other programmable logical devices known under name PLA (Programmable Logic Array).
The PLA, as well as the multiplexers, demultiplexers and the memories micro-electronic, are the result of recent technologies of integration, which also led to the design and the realization of very complex circuits such as the associated microprocessors and their circuits.
This evolution towards the circuits on high level of integration also posed new problems dependant on the assembly of the integrated circuits between them and on their interfacing which is the whole of the principles and the techniques making it possible to connect several electronic systems between them.
In this theory, we will give a general sight on these recent circuits, as on the whole of the problems which are attached to it.
1. - PROGRAMMABLE LOGIC
NETWORKS
1. 1. - COMPLEX INTEGRATED CIRCUITS
The level of integration of the circuits does not cease increasing and one agrees to recognize the following categories of integrated circuits :
S.S.I. (Shorts Scale Integration)
: 1 to 10 transistors per integrated circuit.
M.S.I. (Medium Scale Integration)
: 10 to a few hundreds of transistors.
L.S.I. (Large Scale Integration) : of a
few hundreds with 10 000 transistors.
V.L.S.I. (Very Large Scale Integration) :
more than 10 000 transistors.
The evolution of the integrated circuits was such as the cost by transistor integrated was reduced during twenty last years into one millionth of that initial.
It is from now on possible to concentrate on only one integrated circuit a whole whole of switching functions formerly fulfilled by several integrated circuits. Think for example of the computers of office : towards the end of the Sixties, one started to build them with several tens of circuits S.S.I. and M.S.I. ; today, only one integrated circuit L.S.I. carries out all the operations necessary.
They is because these computers can be diffused with several tens of thousands of specimens which it appeared more advantageous to design and to produce only one integrated circuit gathering all the functions of the computer.
Generally, the manufacturer buys the integrated circuits necessary, the accessories mechanical, electric, the bill-posters and carries out the final assembly of these various elements to build these computers.
The same procedure is usually followed for the manufacture of the digital watches.
For a production in small series, a manufacturer can employ other methods, use standard components in particular.
The factor determining is the quantity of a given product which will be past on the market. In general, when this quantity is rather important, the manufacturer makes carry out an earth phantom circuit (or several) by a manufacturer of integrated circuits.
These integrated circuits are called CUSTOM (customer), because they are developed at the request of a quite precise customer.
The first microprocessor was created in this way.
For a production in small series, the most economic solution consists in using the standard components available on the market. In certain cases, there are several solutions to fulfill a function. For example, one can either conceive a combinative network, or to use ROM or multiplexers, like that was indicated in the preceding theories.
In general, it is preferable to use more complex integrated circuits in a number restricts rather than a great quantity of less complex integrated circuits. Indeed, the cost of cost of a complex circuit (for example L.S.I.) is hardly higher than that of a simple circuit (S.S.I.).
It should be noted, in addition, that a circuit L.S.I. can be definitely more expensive than a circuit S.S.I. in the first phase of production of this circuit because the cost is directly related to the produced quantity. As figure 1 indicates it, the cost price decreases very quickly when the production increases.
The complex integrated circuits thus have several advantages; they can replace several less complex integrated circuits, they make it possible to reduce the dimension of the printed circuits, to facilitate the operations of assembly and finally to decrease the cost price.
We can also note that in the total cost of a microelectronic system, the price of the integrated circuits accounts for approximately 10 % of the total amount, the 90 % remainders being distributed between the various following stations :
Printed circuit,
Connectors,
Insertion and welding of the integrated circuits,
Connections,
Food,
Frame,
Condensers of decoupling,
Test of the system,
This manufacturing cost are added the expenses relating to the study of the electronic system, storage of the finished products and the components of the system, with the administration, etc…
It was calculated that the sum of all the expenses, in the case of an average numerical system, is equal to approximately twenty times the cost of the integrated circuits composing this system. If for example, the price of the component is of one euro, the total cost price will be of twenty euros.
Thus the total cost of a system is a function of the number of integrated circuits which make it up even if it is not directly proportional to this one.
On the graphics of figure 2, one sees that a system made up of 200 integrated circuits costs 2 units and that that requiring 800 integrated circuits totals 4 units.
The number of integrated circuits is multiplied by 4 whereas the cost of the system only doubles.
So now the two systems were integrated in only one circuit, their costs total would be about equivalent since the two integrated circuits would practically return at the same price.
These various concepts are well-known producers of integrated circuits as well as theirs customers. Nevertheless, there is a disadvantage : the complex integrated circuits are very specialized and very varied. Consequently, they are generally produced in quantity smaller than the standard circuits.
Under the pressure of these various problems, one sought to design circuits on high level of integration, but which can fill of the very varied functions. This led to the design of the PLA or Programmable Logic Networks.
1. 2. - PROGRAMMABLE LOGIC NETWORKS (PLA)
The PLA
were conceived on the basis of the principle that any switching function can be
written in the form of a sum of mintermes (canonical
form). That is to say for example the function : F = 
bd
+ ab
+ a
cd.
This function is the sum of the three
mintermes following : bd,
ab
and acd.
The PLA make it possible to generate a certain number of mintermes starting from n variable and to carry out the sum of these mintermes.
Figure 3 represents the fundamental structure of a PLA.
Each door AND (A, B, C, D, E) at five entries makes it possible to generate a minterme starting from the five variables of entry (I0, I1, I2, I3, I4).
Each door OR (A', B', C') at four entries makes it possible to carry out the sum of the mintermes necessary to obtaining a definite switching function.
The circuit is laid out in form of matrix with horizontal and vertical connections.
In the higher part, the horizontal lines represent the entries I0, I1, I2, I3 and I4 of the PLA and the vertical lines correspond to the entries of the doors AND.
Initially, the horizontal and vertical lines cross without contact between them. The programming will consist in later on joining together a horizontal line with a vertical line in an assemblage point symbolized on figure 3 by a point.
The logical state of the exit of a door AND thus corresponds to the value of a minterme.
It will be enough, during the programming, to join together the exits of the doors AND that one wishes at the entries of the doors OR in order to carry out the logical sum as of the these mintermes.
In the example of figure 3, one “created” thus three combinative networks ; their respective exits being the three exits F1, F2 and F3.
The circuit having for F1 exit is formed with the door OR (A') and with the doors AND A and B ; that having for F2 exit is formed with the doors B', A and C ; finally, that having for F3 exit is formed with the doors C', D and E.
Figure 4 represents the first of these three combinative circuits.
The switching function F1 is written :
In general, the programming of PLA is carried out by the manufacturer starting from the data provided by the customer.
This last, can for example, to provide a table of operation relating to the problem to be solved.
We will examine a voluntarily simple example starting from the table located figure 5.
It is necessary to constitute five mintermes. One thus needs at least five doors AND for three entries (there are three variables). It is necessary also two doors OR since there are two functions (F1 and F2) to generate.
The PLA programmed to answer the problem arising is given figure 6.
You notice that it AND noted B is not used. Indeed, in the table of operation of figure 5, with the second line, you note that the two exits F1 and F2 are with the state L, therefore it is not necessary to cable the entries of the door B.
Finally, four doors AND are sufficient to solve the problem arising.
It would be possible to solve this problem by using a ROM. Theoretically, a ROM would be needed having three entries and two exits is a ROM memory whose capacity of 23 (possible combinations with three entries) would be multiplied by 2 (a number of exits), that is to say 8 x 2 = 16 bits.
In the case of a PLA, one defines the capacity of matrix which is equal to the product of the number of doors AND by the number of doors OR. This capacity is expressed out of bits. In this case, it is of 4 x 2 = 8 bits.
The advantage of the PLA compared to the ROM is manifest if one considers a PLA at 14 entries and 8 exits, available on the market.
Let us consider a PLA comprising 96 doors AND, which allows already many possibilities, for example the constitution of 96 mintermes. The capacity of matrix of this PLA is equal to 96 x 8 = 768 bits.
A ROM equivalent should have a capacity of 214 x 8 = 131 072 bits.
A PLA is thus much more advantageous than a ROM. Indeed, in the case of the latter, it is necessary to take account of all the possible combinations of the entries : with 14 entries, one thus needs a ROM with 214 = 16 384 addresses, while with a PLA one is interested only in the combinations given by the table of operation which are necessary to solve the problem.
1. 3. - FPLA
As the manufacturers conceived and produces the PROM after the ROM, the FPLA (Field Programmable Logic Array = programmable logic networks by fuses) appeared after the PLA.
Their principle remains the same one as that of the PLA. The FPLA are easily programmable by the user. It is enough for that to have an apparatus to be programmed which is often a simple programmer of PROM.
The principle of the programming of these FPLA consists in dissolving fuses at the adequate places by making them cross by a short overcurrent of current, exactly as one proceeds with memories PROM.
Figure 7 represents the diagram of a
FPLA already programmed. The fuses are
represented by the symbol 
.
The FPLA represented has 16 noted entries I0 with I15 and 8 noted exits F0 with F7.
For each entry of the FPLA, there are two horizontal lines; the signal present on one being complementary to that present on the other, as indicates it the following symbol :
The point S (like, S', S"…) is the exit of one AND consisted diodes in parallel.
If one wants to represent the first AND of FPLA, one obtains the diagram of figure 8.
This first minterme can be written as follows :
S = I0 .
1
In the same way, the second minterme (left) will be written :
S' = I0 . 0
. I1 . 1...
I15 . 15
It is quite obvious that S' = 0 for all the combinations of the variables of entry.
OR are consisted transistors in parallel. The first OR corresponding to the F0 exit can be represented as indicated figure 9.
The F0' exit of OR is equal to F0' = S' + S".
The door OR Exclusive makes it possible to reverse the output signal of OR corresponding. It is enough for that to dissolve the fuse and this entry is then at the logical level H. It is the case of the F1 exit (figure 7).
Example :
There is an entry of noted order 
(initial of Enable Chip = validation of case). It validates the
eight exits when it is on the level L. On
the other hand, when this entry is on the level H,
eight exits are with the state high impedance (left tri-state).
1. 4. - FPLA WITH
MEMORY
Another type of logic network also developed, the FPLA with memory.
This FPLA has a register, generally made up by a unit of synchronous rockers of type RS.
This register allows the establishment in the FPLA of a sequential logical circuit. The state of the exits east at the same time function of the state of the entries and the logical state of the exits before the face of clock.
The synoptic one of figure 10 represents a FPLA with memory.
Thanks to the register, the data present at exit of the FPLA are reintroduced at the entry of the network of doors to the face of clock according to.
The diagram of figure 11 is synoptic more developed of a FPLA with memory called FPLS (Field Programmable Logic Sequencer).
The buffer is a logical unit which collects at the same time the data present on the 16 principal entries and the 6 exits of the register of memorizing.
The register of exit is used to maintain the data between two clock pulses.
One in addition finds the network of doors AND and OR characteristic of the PLA.
1. 5. - ARRAY SPOILS
Sometimes, the PLA described in the preceding paragraphs, are unsuited to solve certain problems; either that they are not sufficiently flexible of employment, or which should be carried out a significant number of rather complex circuits.
A first solution consists in conceiving specific customs or integrated circuits.
One second solution consists in using circuits whose principle is intermediate between that of the PLA and that of the customs and that one names Gate Array (network of logical doors) or FPGA (Field Programmable Gate Array).
These circuits consist of a significant number of doors NAND generally located between 500 and 2 000.
Technology employed is, either technology TTL S (Schottky), or technology CMOS.
The programming consists in connecting between them doors NAND in order to constitute the suitable logic network.
The advantage of Gate Array lies in the fact that one can produce it on a large scale for varied applications.
An integrated circuit of this type can replace to 50 integrated circuits S.S.I. and M.S.I.
Array Gate, as the PLA is programmed by the manufacturer starting from the specific problem suggested by the customer. All the circuits which we have just seen, FPLA, FPLS, and FPGA are sometimes called IFL (Integrated Fuse Logic = logical by integrated fuses).
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