Various
types of rockers JK |
Dynamic
parameters of a synchronous rocker |
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Created it, 06/09/09
Update it, 06/09/18
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3. - MAIN ROCKER JK SLAVE
3. 1. - NOTATION SYMBOLIC
MAIN rocker JK SLAVE is another rocker of the MAIN type SLAVE. As shown in the figure 29, rocker JK has two noted entries J and K whereas the rocker D MAIN SLAVE has only one of them.
One finds the entry of clock CLOCK,
entries of handing-over with 0 and
handing-over with 1 the complementary CLEAR
and PRESET and exits Q
and 
of the rocker D MAIN SLAVE.
3. 2. - STRUCTURE AND PRINCIPLE OF OPERATION
MAIN rocker JK SLAVE is elaborate starting from a rocker D MAIN SLAVE. It is enough to add a combinative network on the entry D (see figure 30) to obtain rocker JK.
According to the state of the entries J and K, the exit S of the combinative network connected to the entry D of the rocker D MAIN SLAVE presents one of the four states indicated to the figure 31-a. One is led to the truth table of the figure 31-b which gives the logical state of S according to the possible combinations of the logical states of the entries J, K and Q.
Let us draw the picture of Karnaugh (figure 32) to find the equation simplest of S.
.gif)
The two regroupings appearing in this table make it possible to find the equation logical of S following :
S = J
+ 
Q
By using doors NAND, the following combinative circuit (figure 33) can provide the signal S :
3. 3. - EXAMINATION OF THE FOUR OPERATING MODES ACCORDING TO THE TRUTH TABLE OF THE FIGURE 31-a
If J =
0 and K = 0, then S
= D = Q. That means that the logical state present in D
is the same one as that of the exit Q.
It cannot thus y have swing at the time of the active face of the clock and
the state of the exits Q and
remains unchanged.
If J = 0 and K = 1, then S = D = 0. The logical state that rocker JK at the time of the active face of the clock memorizes is the logical state 0. It is the handing-over with 0 of the rocker which is thus carried out in a synchronous way in opposition to the entry CLEAR which it, is priority and asynchronous.
If J = 1 and K = 0, then S = D = 1. The logical state that rocker JK at the time of the active face of the clock memorizes is the logical state 1. It is the handing-over with 1 of the rocker which is also synchronous.
If J =
1 and K = 1, then S
= D =
. The logical state which is memorized at the exit Q
at the time of the active face of the clock is that of the exit .
Thus with each active face of the
clock, the exit Q rocks to take the state of
and vice versa. This operating mode already seen with the rocker D
MAIN SLAVE is mode TOGGLE. It is
the divider of frequency by 2, the exits Q
and
are at a frequency 2 times smaller than the frequency of the clock signal.
3. 4. - TRUTH TABLE AND CHRONOGRAM
The complete operation of MAIN rocker JK SLAVE is summarized by the truth table of figure 34.
The first three lines of this table indicate that entries CLEAR and PRESET are priority and active on a bottom grade. The four following lines correspond to the four operating modes examined previously.
To illustrate this truth table, let us examine the chronogram of figure 35.
One notices on this figure that each face going up of entry CLOCK is affected of an arrow directed upwards. That indicates that examined rocker JK commutates on the rising face. It is supposed that entries CLEAR and PRESET are inactive because one applies the logical state 1 permanently to them.
Right before the first active face of the clock, the entries J and K are to 0. Thus at the time of this face, the rocker does not commutate and the exit Q remains in the state where it is, i.e. here state 0.
Before the application of the second face going up of the clock, the entry J passes to state 1. The exit Q thus passes to state 1.
With the third active face of the clock, J = 1 and K = 0. The rocker which was with state 1 remains in this state.
With the fourth active face of the clock, J = 0 and K = 1. The rocker commutates to pass to state 0.
With the fifth active face of the clock, J = 1 and K = 1. The rocker thus commutates to pass in a state complementary to the preceding state, that is to say state 1. It is mode TOGGLE.
With the sixth active face of the clock, J = 1 and K = 1. The rocker commutates again to pass to state 0 (TOGGLE).
With the seventh active face of the clock, J = 0 and K = 1. The rocker which was with state 0 remains in this state.
With the eighth active face of the clock, J = 0 and K = 1. The rocker remains with state 0.
With the ninth active face of the clock, J = 1 and K = 0. The rocker thus passes to state 1.
With the tenth active face of the clock, J = 0 and K = 0. The rocker does not change a state and thus remains with state 1. It is the position memory.
3. 5. - VARIOUS
TYPES OF ROCKERS JK
Contrary to rocker JK
described previously, a majority of rockers JK
are sensitive to the downward faces (
)
clock signal and not to the rising faces (
).
One finds also rockers JK MAIN SLAVE whose transfer of the data is carried out in two times. On the face going up of the clock, one memorizes the data in the MASTER, then this one is transferred to the exit from the SLAVE on the downward face. In the truth tables of these rockers, this operating mode is announced in the column affected to entry CLOCK by the symbol P.
As in the case of the rocker D, entries PRESET and CLEAR can be active with state 0 or with state 1 according to the constitution rocker interns.
There are also rockers JK at multiple entries. Figure 36 represents of them one which has six noted entries J1, J2, J3, K1, K2, K3.
The operation of such a rocker is similar to that of a traditional rocker JK. It is enough to replace J and K by :
J = J1 . J2 . J3
K = K1 . K2 . K3
This type of rocker was used to produce meters. Since those are available in the form of integrated circuits, rockers JK at multiple entries are not employed any more.
4. - DYNAMIC PARAMETERS
OF A SYNCHRONOUS ROCKER
The manufacturer defines a certain number of dynamic parameters which one must respect to obtain a correct operation of the circuit used.
4. 1. - TIME OF PRESETTING (SET UP TIME IN ENGLISH) OF A DATA ON AN ENTRY DEPENDANT ON THE CLOCK
The time of presetting is the minimal time during which the data present on the entry must remain stable before the active face of the clock signal so that this one is recognized. If this time is not respected, the data will not be taken into account by the circuit.
Figure 37 illustrates the time of presetting (tsep up) when the data to be memorized is on the level L.
V ref. corresponds to the tension of swing of the doors of the circuit :
V ref. = 1,5 V in standard
technology TTL.
V ref. = 1,3 V in technology TTL
- LS.
V ref. = VDD / 2 in technology C.MOS,
VDD being the supply voltage of the circuit.
Figure 38 illustrates the time of presetting when the data to be memorized is on the level H.
The two chronograms of figures 37 and 38 are often joined together in only one in the catalogs of manufacturers, as shown in the figure 39.
The hatched periods indicate that the data can vary from one level to another without there being of influence on the behavior of the circuit.
4. 2. - TIME OF MAINTENANCE (HOLD TIME IN ENGLISH) OF A DATA ON AN ENTRY DEPENDANT ON THE CLOCK
The time of maintenance is the minimal time during which the data present on the entry must remain stable after the active face of the clock so that this data is recognized.
Figure 40 illustrates the time of maintenance (thold) when the data to be memorized is on the level L.
Figure 41 illustrates the time of maintenance when the data to be memorized is on the level H.
The two chronograms of figures 40 and 41 can, in the same way that previously, being joined together in only one, as shown in the figure 42.
In the catalogs of manufacturers, the two chronograms which represent times of presetting and maintenance are gathered in only one, as shown in the figure 43.
4. 3. - TRAVEL TIME OF AN ENTRY A AN EXIT
4. 3. 1. - TRAVEL TIME “tpLH”
The travel time tpLH is the time which passes between the moment when the entry of order becomes active and the moment when the exit passes from the level L on the level H.
The entry of order can be the entry of
clock, entry CLEAR or entry PRESET.
This time noted tpLH is specified for a
given entry (CLOCK, CLEAR or PRESET)
and a given exit (Q or ).
In practice, this time corresponds to the delay brought by the internal doors of the circuit.
Figure 44 illustrates time tpLH.
4. 3. 2. - TRAVEL TIME tpHL
The travel time tpHL is the time which passes between the moment when the entry of order becomes active and the moment when the exit passes from the level H on the level L.
Figure 45 illustrates this time tpHL.
4. 4. - MAXIMUM FREQUENCY OF THE CLOCK
This limiting frequency of operation fmax is due to the delay brought by the doors of the circuit. It corresponds to one minimal period 1 / fmax of the clock signal as figure 46 indicates it.
After having examined the principles of operation and the characteristics of the rockers D and JK, let us make a brief review of the integrated circuits available on the market.
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