Created it, 06/09/09
Update it, 06/09/22
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In this theory, we will examine the circuits with shift called also registers with shift.
These circuits are generally made of synchronous rockers connected one following the other and ordered by the same clock signal.
The state of the first rocker shifts with the following rockers from where the name of “circuits with shift”.
They are very much used as circuit of temporization, like circuit of memory and data processing.
An important application of the registers to shift is the transmission set of logical data.
We will see that the registers with shift can be presented in various forms according to access's to the entries and exits.
1. - REGISTER
AT ENTRY SERIES AND PORT SERIAL
1. 1. - HOW DOES A REGISTER WITH SHIFT FUNCTION ?
To include/understand the operation of the registers with shift, in particular the register at entry series and port serial, we will take into account the very simple circuit of figure 1.
We deduce, by observing this figure, that the LED ignites if the switch is commutated to the top, which makes lead the transistor.
On the other hand, the LED is extinct if the switch is commutated to the bottom what blocks the transistor.
Thus, the LED follows accurately and immediately the orders coming from the switch; each opening or closing of this one produced an instantaneous effect on the state of the LED.
In other words, information on the state of the switch is transmitted immediately (put aside switching time of the transistor).
Let us observe now the circuit of figure 2. A synchronous rocker of type D is inserted between the switch and the LED.
In this case, information on the state of the switch is not transmitted immediately to the LED, because it is necessary to apply an impulse to entry CLOCK.
The exit Q of the rocker is put at the state determined by the position of the switch each time an impulse is applied to entry CLOCK.
We are thus informed about the state of the switch with a certain delay.
Let us modify now the circuit while making pass the number of the rockers to four as illustrated on figure 3.
In this new circuit, the rockers are connected in cascade; the exit of is connected to the entry of the following one.
Entries CLOCK, on the other hand, all are connected between them. Thus, a single entry of clock orders the four rockers simultaneously.
Since four rockers are inserted between the switch and the LED, one thus needs four clock pulses to transmit information on the state of the switch of the entry for the exit of the circuit where the LED is.
The first impulse transfers information from the entry to the exit of the first rocker, the second transmits it to the exit of the second rocker and so on until the fourth.
Information thus shifts by being propagated entry of the first rocker at the exit of the fourth rocker at the end of four clock pulses.
The circuit of figure 3 constitutes a register with shift.
1. 2. - REGISTER WITH SHIFT USED AS CIRCUIT OF TEMPORIZATION
We will see now with what can be used this type as circuit which, apparently, does nothing but complicate the transmission of the ordering of the switch.
An application of the register to shift consists in using this one like circuit of temporization.
Let us take again the circuit of figure 3 and suppose that the exits of the four rockers are on the bottom grade and that we commutate the switch with the positive tension.
We note, according to figure 4, which enters the moment t0 where we close the switch (position “+”) and the moment t4 where the LED ignites, it runs out three periods of clock. The interval t0 at t4 is the time put by the state of the switch to arrive at exit of the assembly where it determines the lighting of the LED.
If we connect the indicating circuit to LED at the exit of the third rocker, temporization obtained is two periods and one period of clock if it is connected to the exit of the second rocker.
We can also exploit the frequency of the clock pulses to vary temporization.
In short, while exploiting on the number of rockers and the frequency of the clock signal, it is possible to obtain a temporization of any duration.
1. 3. - REGISTER A SHIFT USED AS DELAY ELEMENT
In the example that we have just examined, the switch is commutated with the positive tension at the beginning of the experiment and remains in this position until the end of this one.
After four clock pulses, the exit passes thus on the level H.
But nothing prohibits to commutate the switch between a clock pulse and the following one.
In this case, the exit of the circuit follows these commutations accurately, but with a delay of three periods of clock corresponding to four active transitions from the clock signal.
Figure 5 shows the chronogram of signals D1, Q4 and CLOCK according to time.
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It appears clearly that information presents in D1 is found in Q4 after four clock pulses.
The examined register is simplest of the circuits with shift.
It is called register with shift with entry series and port serial or more simply register series-series.
This name comes owing to the fact that information relating to the state from the switch, are presented at the entry of the circuit sequentially one after the other, i.e. in series. The D1 entry constitutes the entry series of the register.
In the same way, they present at the exit one after the other, therefore in series. The Q4 exit constitutes the port serial of the register.
2. - ENTERED REGISTER A SERIES AND PARALLEL PORTS
2. 1. - OPERATION
If we remove the indicating circuit with LED and the switch of entry of the circuit of figure 3, there remains only the register with shift series-series itself whose we saw two applications.
We now will analyze of it a third, in which the register with shift is used as and dephasing delay element of a rectangular signal.
For that, it is advisable to modify the circuit like illustrated on figure 6, i.e. to add three other intermediate exits in correspondence with the exits of each rocker.
We apply to the D1 entry of the circuit a rectangular signal of frequency less low than the clock signal applied to entry CLOCK.
At the Q1 exits, Q2, Q3 and Q4 of the register appear four signals identical between them but delayed, i.e. out of phase one compared to the other of a time equal to the period of the clock signal (figure 7).
The explanation of the chronogram of figure 7 is simple :
The rectangular signal at the entry of the circuit is propagated from one rocker to another while shifting of a position to each clock pulse.
These signals thus out of phase can be used to produce repetitive orders. We thus obtain a sequence of signals which can be used to make an automatism whose we will analyze a simple and concrete example.
2. 2. - APPLICATION TO THE SEQUENTIAL CONTROL OF LAMPS
If as in the illustrated example figure 8, we connect four lamps to the four exits of the register, the lamps will ignite sequentially.
Indeed, at moment t1 (figure 7), the Q1 exit passes on the level H and thus the L1 lamp ignites while the other lamps remain extinct.
At the moment t2, the Q2 exit passes on the level H and the L2 lamp ignites (L1 remaining lit).
At moment t3, the Q3 exit passes on the level H and L3 ignites (L1 and L2 also lit).
At the moment t4, two changes occur : the Q4 exit passes on the level H and L4 ignites, but at the same time, the Q1 exit passes by again on the level L and thus the L1 lamp dies out.
At the moment t5, L2 dies out
At the moment t6, L3 dies out.
The cycle describes moment t1 at the moment t6 continues indefinitely.
We can imagine more complicated cycles by increasing the number of rockers of the register.
For example, in the place of the lamps, we can suppose that there are the orders of a machine tool and this in order to automate it.
The register that we have just examined is a register at entry series and parallel ports or more simply a register parallel series.
We now will analyze an integrated register of this type.
2. 3. - ANALYSIS OF A REGISTER PARALLEL SERIES INTEGRATED : 74164
The integrated circuit 74164 is a register with shift at two entries series and eight ports parallel having an entry of clock (CK) and an asynchronous entry of master clear priority (CLR).
The stitching of this circuit is given on figure 9, while figure 10 gives its truth table.
NOTE :
Names Q1n, Q2n, Q3n, etc… which appear in the truth table of the integrated circuit 74164 you are probably unknown. These names mean simply that the exit considered has the state that had the preceding rocker before the blow of clock. For example, in the 3rd line of the table (when A and B are to 1), we read in the Q2 column the state Q1n, that thus means that Q2 is with the state where was Q1 before the blow of clock which made pass Q1 to 1.
3. - REGISTER A ENTERED PARALLEL AND PORT SERIAL
The registers parallel series or series-series make it possible to shift towards the line of information by applying them to one to the entry series.
In other words, the data are available in series, that is to say on only one wire. But it can present the case where several data are available simultaneously.
It is thus necessary to be able to insert these data at the same time in the register ; this is carried out via several entries known as parallel.
The operation which consists in positioning each rocker of the register with the level present on the corresponding parallel entry names loading (English LOAD) of the register. This loading can be made in an asynchronous or synchronous way using an entry of order called SHIFT / LOAD.
If the loading is asynchronous, as soon as the entry SHIFT / LOAD is activated, each exit of the register recopies the state present on its parallel entry.
So on the other hand the loading is synchronous, it is moreover necessary to apply one clock pulse so that each rocker of the register memorizes the preceding state on its parallel entry.
If the entry SHIFT / LOAD is not activated, the register functions in series-series mode.
3. 1. REGISTER ASYNCHRONOUS PARALLEL - SERIES A LOADING
Figure 11 represents a register parallel-series 4 bits (because it comprises 4 stages) whose loading is carried out in an asynchronous way.
Compared to the preceding registers, it appears a combinative network of logical doors. Those act on asynchronous entries CLEAR and PRESET of each rocker.
The loading of the register, operation which consists in positioning the exits Q1, Q2, Q3 and Q4 with the logical levels present on the parallel entries E1, E2, E3 and E4, will be thus asynchronous.
The two shift, operating modes and loading, are differentiated by the entry from order SHIFT / LOAD.
According to the level applied to this entry, the register functions in SHIFT mode, i.e. in shift mode or in mode LOAD, i.e. in loading mode.
3. 1. 1. - EXAMINATION OF MODE LOAD
To carry out the loading (parallel) of the register, it is necessary to apply a level H to the entry SHIFT / LOAD.
Indeed, the doors AND of the network are validated and the entries E1, E2, E3 and E4 act thus on entries CLEAR and PRESET of each rocker.
To include/understand how the asynchronous loading of the register is carried out, let us examine the action of the E1 entry on the first rocker.
Since the entry SHIFT / LOAD is carried on the level H, the logical level applied in E1 is found on entry PRESET of the rocker, while entry CLEAR receives the logical level opposite with that of E1.
Entries CLEAR and PRESET being active on the level H, when E1 is on the level H, entry PRESET becomes active and the Q1 exit of the rocker thus passes on the level H.
So on the other hand, the E1 entry is on the level L, it is the entry CLEAR which becomes active and thus the rocker goes on the level L.
In short, when the entry SHIFT / LOAD is on the level H, the Q1 exit “recopies” the E1 entry.
The same applies to the other exits Q2, Q3 and Q4 which recopy respectively the entries E2, E3 and E4.
As long as we are in phase of loading, the clock signal does not have any influence since one of two entries CLEAR or PRESET is active, therefore priority.
3. 1. 2. - EXAMINATION OF THE SHIFT MODE
Now let us bring back the entry SHIFT / LOAD to the level L. Consequently, entries CLEAR and PRESET become inactive since they go on the level L independently of the level of the parallel entries.
The clock signal becomes dominating and the register functions in SHIFT mode.
With each clock pulse, the data present in D1 is transferred in Q1, that presents in Q1 is transferred in Q2 and so on to the Q4 exit.
It should be noted that the data present in Q4 is lost with each clock pulse.
The data present on E1, E2, E3 and E4 can vary, they do not have any influence on operation in shift mode of the register.
In short, information on 4 bits present on the parallel entries is charged on a high level with the entry SHIFT / LOAD. While bringing back this entry to the level L, information charged shifts towards the line of a notch to each clock pulse.
We now will analyze an integrated register of this type.
3. 1. 3. - ANALYSIS OF AN ASYNCHRONOUS REGISTER PARALLEL - SERIES INTEGRATED : 74165
The integrated circuit 74165 is a register with shift 8 bits at a entry series (ES) and an exit (Q8). It has eight parallel entries (E1 with E8), an entry of ordering of shift and asynchronous loading (SHIFT / LOAD), an entry of clock (CK) and an entry of inhibition (CK INHIBIT). It should be noted that these two entries CK and CK INHIBIT are interchangeable.
The stitching of this integrated circuit is given on figure 12, while figure 13 gives its truth table.
3. 2. - REGISTER SYNCHRONOUS
PARALLEL - SERIES A LOADING
The preceding register made it possible to preposition its contents in an asynchronous way.
We will see now how to carry out the loading of the synchronous register of way.
To obtain this result, it is enough to replace the combinative network of figure 11 by another network acting either on asynchronous entries CLEAR and PRESET, but on the synchronous entries D1, D2, D3 and D4 of the rockers.
Each part of the network specific to a rocker includes/understands an entry of order corresponding to the entry SHIFT / LOAD, two inputs and an exit.
Figure 14 shows how the register parallel-series with synchronous loading is structured.
Each part of the combinative network, located by symbols RL1, RL2, RL3 and RL4 on figure 14, can be comparable with a shunting of logical data.
According to the level of the entry of order, the circuit “will switch” one or the other of the two entries towards the exit. In other words, the exit “will recopy” one of the two entries.
Let us analyze for example, first combinative network RL1 of the assembly of figure 14, the three others being strictly identical to the first.
Let us suppose that when the entry SHIFT / LOAD is with state 0, D1 = ES and that D1 = E1 when the entry SHIFT / LOAD is with state 1 (the reverse being able to exist).
The truth table of figure 15 illustrates the operation of network RL1.
The first line of this table indicates for SHIFT / LOAD = 0, the D1 exit recopies the entry ES whatever the state of E1.
The second line indicates that for SHIFT / LOAD = 1, the D1 exit recopies the E1 entry whatever the ES state.
These two lines make it possible to find the equation of D1 following :
This equation can be also written in the form :
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This new form of the equation of D1 enables us to simplify it according to the theorem of MORGAN with an aim of carrying out network RL1 using doors NAND. We obtain as follows :
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We end thus to the diagram of figure 16.
3. 2. 1. - EXAMINATION OF MODE LOAD
If the entry SHIFT / LOAD is with state 1, the exit of each network is on the same logical level as the corresponding parallel entry.
In other words, D1 = E1, D2 = E2, D3 = E3 and D4 = E4.
We can say that the four entries E1, E2, E3 and E4 are respectively acicular towards the D1 entries, D2, D3 and D4 of the rockers.
The register is then ready to be charged with the levels present on the parallel entries.
It is enough to send a clock pulse on entry CLOCK so that Q1 = E1, Q2 = E2, Q3 = E3 and Q4 = E4.
The loading of the register is thus quite synchronous.
We obtain the equivalent diagram of figure 17.
3. 2. 2. - EXAMINATION OF THE SHIFT MODE
If the entry SHIFT / LOAD is with state 0, the register functions in SHIFT mode or shift.
Indeed, the entry ES is connected through the first network to the D1 entry of the first rocker.
In the same way, the exits Q1, Q2 and Q3 “are connected” respectively to the entries D2, D3 and D4 through the second, third and fourth networks.
We can say that D1 = ES, D2 = Q1, D3 = Q2 and D4 = Q3.
Figure 18 shows the equivalent diagram of the register in SHIFT mode.
With each clock pulse, the contents of the register are shifted of a step towards the line.
The ES data present is memorized in Q1, while the data present in Q4 is lost.
By combining the two operating modes of the register, we can, initially, charge this one with information, then in the second time, shift this one of one or more step towards the line.
We now will analyze an integrated register of this type.
3. 2. 3. - ANALYSIS OF A SYNCHRONOUS REGISTER PARALLEL - SERIES INTEGRATED : 74166
The integrated circuit 74 166 is a register with shift 8 bits at a entry series (ES) and a port serial (Q8). It has eight parallel entries (E1 with E8), an asynchronous entry of master clear priority (CLR), an entry of ordering of shift and synchronous loading (SHIFT / LOAD), an entry of clock (CK) and an entry of inhibition of clock (CK INHIBIT), these two entries being interchangeable.
The stitching of this circuit is given on figure 19, while figure 20 gives its truth table.
NOTE :
Contrary to the example chosen for our theoretical explanations, it should be noted that the integrated circuit 74 166 is in mode LOAD when its entry of order SHIFT / LOAD is with state 0, and in SHIFT mode when this same entry is with state 1.
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