Universal
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Analyze
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Dynamic
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Created it, 06/09/09
Update it, 06/09/22
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6. - BIDIRECTIONAL REGISTER
6. 1. - SYNCHRONOUS REGISTER PARALLEL-SERIES CABLED FOR THE SHIFT ON THE LEFT
The register parallel-series with synchronous loading allowed prépositionner its contents, then to carry out a shift on the right this one thanks to the entry of order SHIFT / LOAD.
Information shifted Q1 exit towards the Q4 exit.
It is sometimes useful to be able to shift information in a register in the other direction, i.e. Q4 exit towards the Q1 exit.
It is then about the shift on the left.
Let us see which are the connections to be carried out on the register to obtain the shift on the left its contents.
Let us connect the Q4 exit to the E3 entry, the Q3 exit at the E2 entry and the Q2 exit at the E1 entry.
We end thus to the diagram of figure 30.
Let us carry the entry SHIFT / LOAD (S / L) on the level H. Ainsi, in same time, the E4 entry is “connected” to the entry D4, the Q4 exit at the D3 entry, the Q3 exit at the D2 entry and the Q2 exit at the D1 entry.
From now on, if we enter information by the E4 entry, those will shift with each clock pulse of the Q4 exit towards the Q1 exit. We assist well with the shift on the left information. The E4 entry becomes the left entry series and the exit Q1, the left port serial.
Figure 31 shows the equivalent diagram of the circuit obtained.
So on the other hand the entry SHIFT / LOAD is carried on the level L, we obtain a shift on the right contents of the register.
The entry ES constitutes the entry right series of the register and the Q4 exit the right port serial.
In short, the examined register functions either in shift mode on the right, or in shift mode on the left.
Only, it does not function any more in mode LOAD.
To obtain the three operating modes mentioned above, it is necessary to call upon the universal register.
6. 2. - UNIVERSAL
REGISTER
6. 2. 1. - DIAGRAM AND EXAMINATION OF THE FOUR OPERATING MODES
To differentiate the three following modes, parallel loading, shift on the right, shift on the left, two entries of order are necessary.
Those, called S0 and S1, make it possible to differentiate four operating modes. However, three modes are envisaged. The fourth will make it possible to inhibit the action of the clock.
The table of figure 32 indicates the correspondence between each operating mode and each combination of the entries S0 and S1.
To obtain these four modes, it is necessary to replace each network of shunting of the preceding register by another more complex.
If we add the network of inhibition of clock, we obtain the diagram of the universal register four bits represented on figure 33.
Each logic network RL1, RL2, RL3 and RL4 has as a role to switch an entry among the three which are applied to him towards the entry D of the rocker with which it is associated.
This “commutation” is carried out by the two entries S0 and S1.
Let us examine each operating mode of the register.
If S0 = S1 = 0, the clock signal applied to
entry CLOCK does not have an action. The
exits of the register remain on their state.
If S0 = 0 and S1 =
1, then D4 = ESG ; D3 = Q4 ; D2 = Q3 ; D1 =
Q2.
The register “is thus cabled” to carry out the shift on the left.
Information to be shifted is applied to the entry left series (ESG). The port serial is carried out on the Q1 exit which is thus the left port serial.
If S0 = 1 and S1 =
0, then D1 = ESD ; D2 = Q1 ; D3 = Q2
and D4 = Q3.
The register “is thus cabled” to carry out the shift on the right.
Information to be shifted is applied to the entry right series (ESD). The port serial is carried out on the Q4 exit which is thus the right port serial.
If S0 = 1 and S1 =
1, then D1 = E1 ; D2 = E2 ; D3 = E3 ; D4 =
E4.
The register “is thus cabled” to carry out the parallel loading.
Information to be charged is presented on the parallel entries E1, E2, E3 and E4. They are memorized, with each active face of clock, on the Q1 exits, Q2, Q3 and Q4 of the register.
We see that all the operation of a universal register rests on the operation of logic networks RL1, RL2, RL3 and RL4. It is thus necessary to give a further information on those.
6. 2. 2. - EXAMINATION OF A LOGIC NETWORK
The four networks of shunting of the examined register are identical. Let us analyze the first, in fact RL1. It must correspond to the truth table of figure 34.
The first line of this table indicates that for S0 = 0 and S1 = 1, the D1 entry recopies the Q2 exit : it is the shift mode on the left.
The second line indicates that for S0 = 1 and S1 = 0, the D1 entry recopy entry ESD : it is the shift mode on the right.
The third line indicates that for S0 = 1 and S1 = 1, the D1 entry recopies the E1 entry : it is mode LOAD.
From this table, we can directly extract the equation from D1 :
D1 =
0
. S1 . Q2 + S0 . 1
. ESD + S0 . S1 . E1
This equation leads us to the combinative network of figure 35 providing the D1 data.
6. 2. 3. - EXAMINATION OF THE NETWORK OF INHIBITION
It remains to examine the network of inhibition which, starting from entries S0, S1 and CLOCK, generates the clock signal of the four rockers.
For the combination S0 = S1 = 0, entry CLOCK must be inactive, i.e. it should not present any active transition from level on the four entries of clock.
For example, let us block in a logical state 1 the exit S of this network when this combination of S0 and S1 arises.
For the other combinations of S0 and S1, the exit S of the network of inhibition must “recopy” entry CLOCK.
All that is translated in the truth table of figure 36.
We are led to the table of Karnaugh of figure 37.
The two groupings of the table of Karnaugh give us the equation of S following :
The circuit of figure 38 can provide the signal S :
The fact that the clock signal results from a combinative network present a disadvantage.
Indeed, if one has suddenly changed S0 or S1 when entry CLOCK is with state 0, a transition from logical level can occur at the exit S. That can thus cause an active face of clock on the rockers of the register whereas entry CLOCK remained inactive. Let us take an example where this case occurs.
Let us suppose that S0 = 0, S1 = 1 and CLOCK = 0, thus S = 0 and carry the S1 entry to state 0. So the entries S0 and S1 being with state 0, the exit S of the network passes to state 1.
In short, the entry CLOCK having remained inactive, when S1 passed from state 1 to state 0, the exit S passed from state 0 to state 1.
We thus obtain an active face on the entries of clock of the four rockers, whereas entry CLOCK remained with state 0.
To avoid that, the S0 entries and S1 should change state only when entry CLOCK is with state 1.
Thus, the exit is forced with state 1, whatever the variations of S0 and S1.
6. 2. 4. - ANALYSIS
OF A UNIVERSAL INTEGRATED REGISTER : 74 194
The integrated circuit 74 194 is a register with bidirectional shift 4 bits having two entries of order (S0 and S1), an entry of clock (CK), an input series for the shift on the left (ESG), an input series for the shift on the right (ESD), four parallel entries (E1 with E4), an asynchronous entry of master clear priority (CLR) and four parallel ports (Q1 with Q4).
The stitching of this circuit is given on figure 39, while figure 40 gives its truth table.
For the second line of the truth table of the integrated circuit 74 194, there is no change of the state of the exits when CLOCK is with state 0 provided that the entries S0 and S1 do not change a state.
7. - DYNAMIC
REGISTER
The registers seen until now are of static type because the information which are stored there can be stored indefinitely with the proviso of not disconnecting the food.
This is very convenient because we can constantly read information which was charged, but it appears a disadvantage from the integration point of view.
Indeed, each stored binary data requires a whole rocker.
So the integration of static registers of great capacity (more than 1000 stages) is limited.
Beyond, we have recourse to the circuits with shift of the dynamic type.
Those cannot memorize information indefinitely and must thus make them ravel. This characteristic comes owing to the fact that each storage element is not any more one rocker of the conventional type, but a circuit which memorizes information thanks to the stray capacities of transistors MOS.
Figure 41 shows the diagram of a dynamic stage of register. Each stage as this one can store a logical data.
The capacities CE, CI and CS of figure 41 are known as parasites because they are usually undesirable. They correspond to the capacity of grid of transistors MOS.
Normally, those must be weakest possible because they disturb the normal operation of the circuit (increase in the travel time).
In our case however, they are used to store the information in the form of stored loads.
These capacities can be charged or discharged. A capacity charged corresponds to positive information (logical state 1) and a capacity discharged with negative information (logical state 0).
Let us suppose that the entry E is subjected to the bottom grade (L). Transistor T1 is thus blocked.
When the entry of clock CK1 passes on the level H, the T2 transistor is made conducting and thus load with + Vcc capacity CI.
Consequently, transistor T3 is conductive and it thus discharges the capacity CS, Si this one was charged.
The exit S passes on the level L and we can say that the level L present at the entry E was transferred at exit S. This is illustrated on figure 42.
When occurs a positive impulse on the entry of clock CK2, the transistors T3 and T4 are simultaneously conductive.
On the other hand, from the technological point of view, these two transistors are different and their respective resistance of saturation is such as the potential of the point S is much closer to zero than of the tension + Vcc : the exit S thus remains at the logical level L.
So now the entry E is subjected to the level H, transistor T1 starts to lead. Capacity CI is discharged and item I is thus carried on the level L as the chronogram of figure 43 shows it.
When occurs a positive impulse on the entry of clock CK1, two transistors T2 and T1 are saturated simultaneously and as they are realized technologically in the same way that the couple T4-T3, item I are maintained at the logical level L in spite of the conduction of T2.
With the following clock pulse on CK2, the T4 transistor starts to lead and charges the capacity CS on the level H.
The exit S thus passes on the level H and the level H present at the entry E was transferred at exit S.
In short, in a dynamic stage of register (here with two phases of clock), a data applied to the entry is found at the exit when one applies two impulses CK1 and CK2.
It is necessary however that signals CK1 and CK2 are at a sufficient frequency (approximately 10 kHz) so that the stray capacities of transistors MOS do not have time to take care or to discharge between two successive impulses.
The next theory will treat meters and dividers of frequency.
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