Created it, 06/10/19
Update it, 06/10/25
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4. - FIRST EXPERIMENT : “EXAMINATION OF A CIRCUIT LATCH”
The English term “latch” meaning “bolt, latch” is used to indicate a circuit of memory in general. The rocker D used in practice preceding can function as synchronous latch. It indeed memorizes the logical state present on the entry D at the moment of the positive transition applied to entry CLOCK.
With the handling which will follow, you will check the operation of the integrated circuit CD 4042 container four circuits latch asynchronous of type D. the diagrammatic representation of the asynchronous quadruple latch CD 4042 is indicated on figure 12.
Being given the complexity of the circuit, the electric diagram (as you can observe it) is simply made up by a rectangle from which the connections leave to the various pins. However, each pin is located by a symbol making it possible to include/understand the operation of the circuit as for the rocker of the type D which you know already.
Indeed, the four pins D1,
D2, D3, D4 are as many entries similar to the entry D
(or DATED) of rocker D.
the pins Q1, Q2, Q3, Q4 and 
1,
2,
3,
4
is the complémentées exits of the four circuits latch just like Q
and
is the complémentées exits of rocker D.
There are then two entries of validation C1
and C2 communes with the four rockers. These
two entries have a function similar to the entry C
of rocker R.S.C.
Lastly, marked pins VDD and VSS must be connected respectively to (+) and with (-) of the supply voltage.
4. 1. - REALIZATION OF THE CIRCUIT
a) You ensure that the food is disconnected and still remove all the connections places from there after the last experiment carried out at the time of the preceding practice.
b) Insert the integrated circuit CD 4042 on the matrix, with horse on the central groove, in the position indicated by the figure 13-a by paying attention so that the 16 pins of the integrated circuit are correctly introduced into the contacts of the matrix.
c) While serving to you as the insulated canned wire which you have in your possession, cross of the pieces suitable length and prepare them in the manner that you know now and carry out the connections illustrated by the figure 13-a.
You thus carry out following connections with the pins of entry of the CD 4042.
D1 entry (pin 4) with switch SW0
D2 entry (pin 7) with switch SW1
D3 entry (pin 13) with switch SW2
D4 entry (pin 14) with switch SW3
The exits Q1, Q2, Q3, Q4 of the integrated circuit are connected to the four following LED :
Q1 exit (pin 2) with the LED L0
Q2 exit (pin 10) with the LED L1
Q3 exit (pin 11) with the LED L2
Q4 exit (pin 1) with the LED L3
The complementary exits 1,
2,
3,4
are on the other hand not connected : you point out that the bar above
each symbol of these exits indicates the presence of a signal reversed compared
to the not reversed corresponding exit. Therefore, if for example the Q1
exit is on the level L, exit 1
will be on the level H ; it is the same for Q2
and 2,
Q3 and 3,
Q4 and 4.
The C1
entry is connected to the P0
contact pin 5) and the C2 entry to the mass “0
V” (pin 6).
The connections of the CD 4042 that we have just described are easily controllable on the practical diagram of the figure 13-a like on the electric diagram of the figure 13-b.
On this subject, you point out that it is advised always to consult the electric diagram to check the exactitude of the connections carried out in practice.
In this manner, as you carry out the increasingly complex handling envisaged with the program, you will acquérrez the capacity to pass easily from the practical diagram to the theoretical diagram and vice versa, and especially you will learn how “to read” any electric diagram of logical circuit.
After you to be thus ensured that the assembly carried out corresponds to the electric diagram of the figure 13-b, begin the experiment by conforming you to the following indications.
4. 2. - OPERATIONAL TEST
a) Put the four entries D1, D2, D3, D4 on the level L by commutating four switches SW0, SW1, SW2, SW3 on position 0.
b) Feed the circuit by connecting the crocodile clips black and red to the pile of 4,5 V.
Observe the LED, you note that they all are extinct ; in the contrary case, disconnect the food and re-examine the connections carried out.
c) now Put switch SW0 on position 1 thus applying a level H to the D1 entry : you note that the LED L0 ignites.
d) Bring then each entry remaining to the level H by laying out the corresponding switches the ones after the others on position 1 : you notice that to each entry carried on the level H a level H at exit corresponds indicated by the lighting of the various LED.
With this test, you noted that on each exit of the integrated circuit in question, you find the level present on the corresponding entry. Therefore, if the D1 entry is on the level H, the Q1 exit will be also on the level H ; if D1 is on the level L, Q1 will be also on the level L. the same situation can be checked for each other couple input-output D2-Q2, D3-Q3 and D4-Q4.
e) Now put the four switches on an unspecified position. Put, for example SW0 on position 0, SW1 on position 1, SW2 on position 0 and SW3 on position 1. In these cases, the LED L1 and L3 ignite.
f) Press on the P0 button and commutate the four switches then at will all while maintaining P0 inserted.
By observing the indication of the LED, you note that the exits do not change a state, but that these last preserve well the state which they had before P0 was not actuated, which means that the circuit memorized the situation existing before the action on P0.
By taking account of the preceding observations, it is possible to write the first part of the table of operation of the integrated circuit CD 4042 deferred in figure 14, and that one summarizes as follows :
With the C1
entry on the level L and the C2
entry on the level L, the circuit is “transparent”
:
i.e. the exits reproduce the logical levels of the corresponding entries.
With the C1
entry on the level H and the C2
entry on the level L, the circuit memorizes
the last logical level present on the entry at the moment which
immediately precedes that where the C1 entry
passed from the level L on the level H.
g) Cut off the supply and carry the C2 entry on the level H by disconnecting pin 6 from the CD 4042 from the line connected to the contact (-) and by connecting it with another wire length appropriate to the line connected to the contact (+).
h) Connect the food again and remade the tests carried out previously.
You note this time that the situation was reversed ; when the C1 entry is on the level L, the circuit is insensitive with the changes of levels H and L which appear on the entries. It memorizes the logical level present at the moment when the C1 entry passes from the level H on the level L. With the C1 entry on the level H, the circuit is “transparent”.
Using these last observations, you can supplement the table of operation of the CD 4042 which is thus presented as shown in the figure 15.
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The operation of the quadruple latch that you have just examined can ultimately be summarized as follows :
the circuit has of four entries and four exits.
the state where the exits are depends on the state
of the two entries of order C1 and C2.
if the C1 entry
and the C2 entry are both with the state H
or the state L, the exits reproduce or
recopy the state of the entries.
if the C1 entry
is with the state L, when the C2
entry passes to the state H, the circuit
memorizes the states of the entries.
It is the same when the C1 entry is with the state H and that the C2 entry passes to the state L.
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