Symbols
of the various field-effect transistors |
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Created it, 06/03/17
Update it, 06/03/21
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In this lesson, we will examine the structure and the operation of the field-effect transistor then we will approach the internal composition of the logical doors according to various existing technologies.
1. - THE FIELD-EFFECT TRANSISTOR
There is habit to indicate it by his initial : T.E.C or F.E.T. (Anglo-Saxon term : Field-Effect-Transistor).
It consists of a uniformly doped semiconductor bar (of type P or N), constituting the channel.
On this bar two opposed junctions are carried out, as illustrated on figure 1, of opposite conductibility of that of the channel.
These two zones are connected between them electrically to a called common electrode carry or roast.
An end of the channel receives the name of source, the other that of drain.
The channel is slightly doped, whereas the zones which constitute the grid it are strongly.
The great difference for this transistor, lies in the fact that the junction grid-source is polarized in reverse (tension VGS).
Space drain-source receives a biasing (tension VDS).
The principle of operation is as follows :
In the absence of tension grid-source (VGS),
the channel leads proportionally with the increase in tension VDS.
For a certain value of VDS,
the current ceases growing and becomes constant. It is the tension of
pinching or Vp (tension
of pinch-off).
The current in the channel is called ID and when it reaches saturation, it becomes IDSS.
So now one applies a tension VGS
to space grid-source (polarization of the junction in reverse) and that one
raises, like previously, the value of ID
according to VDS, one notes for this current,
of the lower values.
The Vp tension
is reached earlier and corresponds to a current ID less
low than IDSS.
This new Vp' tension is equal to : Vp' = Vp - VGS
The more VGS increases, the more current ID decreases. Starting from a certain threshold of VGS, current ID cancels itself.
It is generally considered that current ID becomes equal to zero for :
VGS = Vp.
All occurs like if the electric field, created by the opposite biasing of the junction grid-source, decreased the width of conduction of the channel. It is the zone of déplétion or impoverishment.
Figure 2 schematizes this phenomenon.
On figure 3 are carried the important characteristics and points which relate to the TEC.
The zone 
corresponds to the linear part of the characteristic, current ID
grows linearly with VDS (for a given VGS).
This zone is used in commutation.
The zone 
is that of saturation and is used in amplification.
The zone 
is prohibited because it represents the phenomenon of avalanche.
The tension of avalanche is noted BVDG in not BVDS (BV = nervous break-down voltage, which means breaking stress or breakdown).
In fact, it is about the breakdown of the diode drain-grid. This one always occurring for the same difference in tension between the drain and the grid (for a type of definite transistor). This difference is given by the relation :
BVDG = VDS + VGS
When VGS = 0, this tension BVDG is equal to VDS.
If one maintains VDS with the same value and that VGS increases (towards the negative values), BVDG will decrease. It is what appears on the network of characteristics.
In addition, according to types' of transistors, Vp spreads out between 0,5 and 15 volts.
Tension BVDG varies between 3 and 25 Vp times, always according to the type of transistor.
It should be noted that conduction, in this type of transistor, is almost symmetrical. On figure 3, one notes that all the characteristics pass by the origin and that around this one, for weak VDS, the characteristics are prolonged, checking the symmetry of conduction well (for VDS of opposite signs).
Inside some limit, the permutation between drain and source does not involve modification of operation.
However, the electrodes are located by the manufacturer in order to minimize certain capacitive effects, thus making it possible to use this device as well as possible.
These capacities are as follows :
CDS (between drain and source)
CGS (between grid and source)
CGD (between grid and drain)
They are the two most important last. By construction, they are attenuated, obliging the user to differentiate the source from the drain.
In the zone
of figure 3 which corresponds to operation in commutation with VDS
< Vp, the transistor reacts like a variable resistor according to VGS.
The value minimum of this resistance is obtained for VGS = 0 (corresponding to the closed switch) and takes the name of Ron (minimal Resistance at the conducting state).
The maximum value is obtained for VGS > Vp (second state of the switch, i.e. open).
R minimum or Ron : closed switch (VGS = 0)
R maximum : open switch (VGS > Vp).
There is another type of field-effect transistor which bears the name of transistor MOS (Metal - Oxide - Semiconductor) or MOST (T for transistor).
This one is very widespread in the integrated circuits where it tends to spread, at the expense of the bipolar transistor, for reasons of consumption.
Figure 4 represents the structure of such a transistor which differs from the TEC. Indeed, it does not have a junction on the level of the grid, a mask of oxide isolates this one from the channel, from where the name that one gives him sometimes : isolated grid voltage.
Operation is as follows :
By applying a positive tension to the grid, the electrons (carrying minority due to thermal agitation) of the substrate (in the case of figure 4, it is about a material P), are attracted between the material N zones, constituting the source and the drain. At this place, the concentration in electrons constitutes an enrichment which is translated as an inversion of the conductibility of the substrate thus passing from the type P to the type N. A current is established between source and drain.
To the variations of VGS correspond of the variations of ID. In the absence of tension VGS, current ID is very weak (practically no one).
The substrate, in general, is carried to the most negative tension, so that the junctions source-substrate and drain-substrate are polarized in reverse.
This type of MOS is known as enrichment (in Anglo-Saxon : enhancement mode).
Figure 5 represents the structure of a transistor MOS to impoverishment.
The operation of this last is different, in the sense that in the absence of tension VGS, we note a current ID (as for the TEC).
Indeed, the channel consisted a mean material N zone located under the grid, is conductive in the absence of tension VGS. If one applies a negative tension to the grid, the free electrons of the canal zone will be pushed back, by the electric field, in the substrate, which has as a consequence the reduction in ID. If tension VGS is increased, current ID is cancelled.
There still, it seems that the conductibility of material is reversed, by impoverishment of the majority carriers.
If in the absence of tension VGS, one makes so that current ID is maintained at an average value, by applying to the grid a positive tension VGS, the electrons of the substrate (carrying minority -----> thermal agitation) will come to reinforce the conductibility of the fine layer from material N and current ID will become more important.
One thus realizes with this technique of transistors MOS functioning according to two modes :
enrichment
impoverishment.
This operation is made possible because of the insulating layer of oxide which separates the grid from the channel.
Figure 6 represents the characteristics of this type of transistor as well as the zones of use.
These transistors have an impedance of very high entry (due to the insulation of the grid). Resistance in conduction (Ron) is low (a few tens of ohms) and their resistance at the blocked state, very high (several megohms).
These characteristics make it possible, amongst other things, to use them in logic. The entry or control circuit (the grid) is well separated from the output circuit and the two states, blocked or conducting, are very clearly differentiated.
Although the substrate has an obvious action on the conduction of the MOS (less than the grid however), it, in general, is connected internally to the case. It outside is joined together, by wiring, with the source.
Its consumption less than that of the bipolar transistor and its behavior in better tension are as many assets in its favor. On the other hand, it is a little slower. The impedance of entry, very high, makes it vulnerable to the electrostatic loads, which obliges the manufacturers to protect his entry and the users to take more precaution during handling. Once the transistor installed on the circuit, it has there no more risk on this subject.
Figure 7 represents the symbols of these various field-effect transistors.
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