Created it, 06/03/17
Update it, 06/03/22
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With regard to the TTL, figure 28 explains clearly what occurs on the level from the tensions and will enable you to introduce new parameters.
Immunity with the noise.
A standard was established (for each technology), it defines the levels of tension, for the entry and the exit of the operators, who symbolize the two logical states, this in the worst of the cases (limiting tolerance of manufacture, ambient temperature and peak load).
When two operators are connected, the exit of the one on the entry of the other, it is necessary to know the margin which remains for each one of these states in order to evaluate the risk of an unnecessary operation due to external causes (parasitic industrialists, potential of mass fluctuating,…) and to take measurements which are essential from the beginning to avoid any failure.
This is concretized with state 0, or bottom grade of tension, by the difference between the maximum tension which the exit of the preceding operator can take, for this state, and the maximum level that the entry of the following operator will still regard as a bottom grade.
Beyond that, it will interpret it like a change of state and its level of exit will be modified consequently.
In state 1, or high level of tension, this is concretized by the difference between the tension minimum which can take the exit of the preceding operator and the minimum level that the entry of the following will still interpret like a high level.
In on this side, it will consider that it is about a change of state and its level of exit will be modified consequently.
These variations of tension characterize the margins of noise, at the low state and the high state. They determine what one names : immunity with the noise (one calls “noise”, in this case, any interfering signal foreign with the useful signal).
The output voltage in a low state VOL is of 0,4 V.
The tension of entry VIL considered as a low state is of 0,8 V.
The difference between these two
tensions gives us the located zone by 
which is the margin of noise in a low state.
The mini output voltage to state high VOH is of 2,4 V.
The tension of entry considered as a high state is of 2 V.
The difference between these two
tensions gives us the located zone by 
which is the margin of noise in a high state.
The zone 
represents the zone of amplification, in logic, it is an area which it is
necessary to avoid.
Immunity with the noise or margin of noise is very low in TTL (0,4 V in theory). In practice, this margin is considered as being of 1 V on the basis of the principle that there is little risk that a circuit having an exit with the values limit is connected to others whose characteristics of entry would have also limiting values.
This immunity with the noise is important in the choice of a technology for a realization. We will see in a summary table that other technologies can have a better immunity with the noises (or disturbing interfering signals).
Another important parameter, in the assembly of operators is the fan-out (or fan-out = range of exit) or pyramidal factor.
It is about the number of circuits which one can connect at exit without deteriorating, in a significant way, parameters of the circuit.
The exit with assembly totem-pole is carried out to this end.
The current of entry standardized in a high state, IIH is + 40 µA.
The output current in a high state, IOH is of - 400 µA.
This makes it possible to consider, at the high state, the connection of ten circuits on the exit.
The current of entry standardized in a low state IIL is of - 1,6 mA.
The current output in a low state which can be absorbed, is + 16 mA.
One will be able to thus connect, in this case, ten circuits on the exit.
In both cases, the connection of ten operators on the exit of only one is possible.
It is said that the fan-out is 10. Beyond that, one degrades, in a significant way, the signals and there is risk of deterioration for the output circuit.
Another parameter, the fan-in (or fan-in = range of entry) or pyramidal factor of entry, a little different from the precedent in the sense that it indicates the number of circuits which can attack the module in question.
In other words, it is about the number of entries which an operator has.
Certain circuits have an entry of expansion making it possible to increase their fan-in.
You could note that the current of entry in a high state was preceded by a sign +, whereas the current of entry in a low state was preceded by sign -, us already referred there.
It was decided, by convention, which the currents entering the module would be positive (thus preceded by a sign +) whereas those which leave there would be negative (preceded by the sign -) that it is in entry or exit.
It is now necessary to tackle the problem of the transit and reaction times of these assemblies.
Let us return to circuit NAND. Let us place one of its entries at the high level and see what it occurs at exit, when its second entry passes from one state to the other.
For more facility, you defer to the figure 29-a.
On the basis of a stable state at exit (here a high state) and after the appearance of the high level at the Ve entry, we note a time lag td (delay-time) before the output signal does not react. This delay corresponds to the time of modification of the loads on the level of the junctions.
Then, the signal at exit evolves/moves exponentially during the time tf which corresponds to the time of descent (fall-time). This evolution is characteristic of a circuit RC which discharges (resistance of semiconductor material and stray capacities). This zone corresponds in the passing on the line of load of a point of rest to the other. It is the zone of amplification and instability.
A stage follows which corresponds at the second stable state. As long as the Ve entry does not undergo modification, the exit preserves this state.
After removal of the input signal, one notes a time lag ts (storage-time) due to the time of modification of the loads on the level of the junction.
Lastly, increase towards the high starting tr state (small channel-time) which is carried out according to an exponential variation corresponding to the load of circuit RC previously quoted.
The zones tr and tf correspond to displacement on the line of load of the point of operation of A towards B or the reverse (i.e. blocking with saturation or vice versa).
We saw that the speed of transit from one point to another was limited by the capacities of the junctions (more stray capacities), which appears clearly on the figures 29-a and 29-b. These times (tf and tr) are measured between 10% and 90% of the value of the signal.
The figure 29-b represents the output signal for a circuit AND.
By simplification, the manufacturers indicate :
time travel to the decrease of the output signal : tpHL.
travel time to the growth of the output signal : tpLH
Figure 30 illustrates these times which are measured starting from a variation equal to 50 % of the input signal or exit and with a load at exit which is defined (in theory for the TTL, consists of a capacity of 15 pF in parallel with a resistance from 100 to 400 W.
For circuit NAND taken in example, we would find:
tpHL ranging between 7 and 15 ns (ns = 10-9 second).
tpLH ranging between 11 and 22 ns.
This for a load at exit of 15 pF and 400 W.
Lastly, the maximum power consumed by the whole of the case, which can contain several operators, is indicated on the notes. This data is not to neglect, because it makes it possible to determine the power of the food.
It is necessary to keep in mind that the correct operation of the electronic sets is closely related to qualities of their food. With regard to the logical circuits, those will have to be able to support important variations of current in very short times (change of state of the assemblies totem-pole). Decouplings, close to cases, will have to be set up.
It is interesting, in the assemblies, to minimize the number of modules, either for reasons of cost, or for reasons of operation (in order to balance transfer times between two routes).
Sometimes for that, one has recourse to the cabled switching
functions.
For example, if one joins together the exit of two operators, by wiring, one obtains the function: OR cable length.
With the assembly totem-pole, this meeting is not possible.
Figure 31 illustrates why this way of proceeding is not possible (short-circuit of the food).
The manufacturers carry out operators designed for this purpose and who take the name of operators with open collectors.
Those allow the function OR cable length. The figure 32-a represents a circuit NAND with open collector (open-collector).
The figure 32-b illustrates the way of proceeding and the figure 32-c schematizes operation in substituent the transistors of exit by switches (S1 and S2).
Resistance common to the collectors of the transistors of exit must be placed outside.
In this case, there is no more short-circuit on the food, whatever the position of S1 or S2.
Their connection in parallel shows well that it is about the function OR.
In technology TTL, it should well be remembered that this function is not possible that when the operators are at exit : open collector (and by cabling outside the common resistance of collector R).
It is sometimes necessary to order more than ten operators with an exit.
In this case, one has recourse to operators whose exit can inject or absorb more current. It is said that these operators are at bufferized exit. Some fulfill only this function, in this case, they are called buffers.
This exit can be with assembly totem-pole with a resistance series of 30 W instead of 130 W and the transistors of exit are likely to carry a higher current. Their polarization is a little different and the diode is removed.
It can also be with open collector with a more powerful transistor of exit (running collecting more powerful and higher VCE).
The figures 33-a and 33-b represent these two assemblies.
There are several alternatives of the TTL. The purpose of they are, either a reduction in consumption (TTL - L, L = Low-power) but with the detriment the speed of operation (3 MHz only), or an increase this speed (120 MHz) as well as consumption (TTL - S, S = Schottky).
Another alternative of the TTL is technology TTL - LS (Low power Schottky). This one at the same speed of operation as the traditional TTL (approximately 45 MHz) but a consumption 5 times less. It is supplanting the TTL.
It is necessary to announce, moreover, the tri-state TTL (3 states). In addition to the two logical states, a third intervenes to disconnect the operator from the remainder of the assembly by putting the two transistors of exit of the totem-pole at the blocked state (state OFF) or high impedance.
This way of proceeding was born following the technique of the buses from data transmission.
A great number of operators connected on these lines, led to the use of OR cabled, therefore operators with open collectors.
This last being definitely slower than the assembly totem-pole, one had the idea to preserve this last but while disconnecting from the line, all the operators nonconcerned by the transmitted signals, using a signal applied to a special entry and which blocks the two transistors of exit of each one of these operators.
With the realization of the switching functions in technology TTL, this last TECHNOLOGY 2 is completed.
The following will treat these functions but in technology MOS.
We will also speak about different other technologies as well as manufacturing processes from these circuits.
These headings are perhaps not among most attractive but we insist on the fact that technology revêt, for the electronics specialist, a great importance, as well on the plan of the choice of the material as for the comprehension of the transitory phenomena.
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